From cff25a1f8687f4cec13324f7b1579a2e0ee5d2e8 Mon Sep 17 00:00:00 2001 From: Alex Williamson Date: Thu, 17 Jan 2008 12:05:43 -0700 Subject: [PATCH] [IA64] Rearrange IA64_TR_ definitions to use from lower value SDM vol2 4.1.1.1 says that: "software should allocate contiguous translation registers starting at slot 0 and continuing upwards." Signed-off-by: Isaku Yamahata --- xen/include/asm-ia64/xenkregs.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/xen/include/asm-ia64/xenkregs.h b/xen/include/asm-ia64/xenkregs.h index fb62f70c0e..432387ac98 100644 --- a/xen/include/asm-ia64/xenkregs.h +++ b/xen/include/asm-ia64/xenkregs.h @@ -4,10 +4,11 @@ /* * Translation registers: */ -#define IA64_TR_SHARED_INFO 3 /* dtr3: page shared with domain */ -#define IA64_TR_VHPT 4 /* dtr4: vhpt */ +#define IA64_TR_XEN_HEAP_REGS 3 /* dtr3: xen heap identity mapped regs */ +#define IA64_TR_SHARED_INFO 4 /* dtr4: page shared with domain */ #define IA64_TR_MAPPED_REGS 5 /* dtr5: vcpu mapped regs */ -#define IA64_TR_XEN_HEAP_REGS 6 /* dtr6: xen heap identity mapped regs */ +#define IA64_TR_VHPT 6 /* dtr6: vhpt */ + #define IA64_DTR_GUEST_KERNEL 7 #define IA64_ITR_GUEST_KERNEL 2 /* Processor status register bits: */ -- 2.30.2